1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods of forming conductive structures, such as conductive contacts and conductive lines/vias, using a sacrificial material during the process of removing a metal hard mask layer used in forming such conductive structures.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements, such as transistors, capacitors, resistors, etc., to be formed on a given chip area according to a specified circuit layout. During the fabrication of complex integrated circuits using, for instance, MOS (Metal-Oxide-Semiconductor) technology, millions of transistors, e.g., N-channel transistors (NFETs) and/or P-channel transistors (PFETs), are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NFET transistor or a PFET transistor is considered, typically includes doped source and drain regions that are formed in a semiconducting substrate and separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
To improve the operating speed of field effect transistors (FETs), and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the past decades. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs and the overall functionality of the circuit. Further scaling (reduction in size) of the channel length of transistors is anticipated in the future. While this ongoing and continuing decrease in the channel length of transistor devices has improved the operating speed of the transistors and integrated circuits that are formed using such transistors, there are certain problems that arise with the ongoing shrinkage of feature sizes that may at least partially offset the advantages obtained by such feature size reduction. For example, as the channel length is decreased, the pitch between adjacent transistors likewise decreases, thereby increasing the density of transistors per unit area. This scaling also limits the size of the conductive contact elements and structures, which has the effect of increasing their electrical resistance. In general, the reduction in feature size and increased packing density makes everything more crowded on modern integrated circuit devices.
Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same level on which the circuit elements, such as transistors, are manufactured. Rather, modern integrated circuit products have multiple so-called metallization layer levels that, collectively, contain the “wiring” pattern for the product, i.e., the conductive structures that provide electrical connection to the transistors and the circuits, such as conductive vias and conductive metal lines. In general, the conductive metal lines are used to provide intra-level (same level) electrical connections, while inter-level (between levels) connections or vertical connections are referred to as vias. In short, the vertically oriented conductive via structures provide the electrical connection between the various stacked metallization layers. Accordingly, the electrical resistance of such conductive structures, e.g., lines and vias, becomes a significant issue in the overall design of an integrated circuit product, since the cross-sectional area of these elements is correspondingly decreased, which may have a significant influence on the effective electrical resistance and overall performance of the final product or circuit.
Improving the functionality and performance capability of various metallization systems has also become an important aspect of designing modern semiconductor devices. One example of such improvements is reflected in the increased use of copper metallization systems in integrated circuit devices and the use of so-called “low-k” dielectric materials (materials having a dielectric constant less than about 3) in such devices. Copper metallization systems exhibit improved electrical conductivity as compared to, for example, prior metallization systems that used tungsten for the conductive lines and vias. The use of low-k dielectric materials tends to improve the signal-to-noise ratio (S/N ratio) by reducing crosstalk, as compared to other dielectric materials with higher dielectric constants. However, the use of such low-k dielectric materials can be problematic as they tend to be less resistant to metal migration as compared to some other dielectric materials, they tend to be mechanically weaker than other common insulating materials, such as silicon dioxide, that have a higher dielectric constant and they may be more susceptible to chemical attack from various solutions that they are exposed to during processing operations.
One such problem will be discussed with reference FIGS. 1A-1B, which depicts one illustrative prior art method of forming conductive structures to the contact level of an integrated circuit product using a damascene process. FIG. 1A depicts an integrated circuit product 10 comprised of a plurality of illustrative conductive contacts 12 formed in a layer of insulating material 14. The conductive contacts 12 are formed in the contact level of the product 10. Typically, the conductive contacts 12 are conductively coupled to a region or portion of a semiconductor device (not shown), such as the gate electrode and/or the source/drain regions of a transistor device. In the depicted example, each of the conductive contacts 12 may be comprised of one or more barrier layers or liners 12A, e.g., titanium nitride, and a bulk conductive material 12B, e.g., tungsten. An etch stop layer 16 is formed above the layer of insulating material 14. The layers 14, 16 and the conductive contacts 12 may all be considered to be part of the contact level layer 15 of the integrated circuit product 10. Electrical connections have to be made to the conductive contacts 12 for the product 10 to operate. Thus, another metallization layer 17 is formed above the contact level layer 15. In the depicted example, formation of the metallization layer 17 involves the formation of the first conductive via (V0) and an illustrative metal line of the first metallization layer (M1). As noted above, the product 10 will typically comprise several metallization layers, e.g., multiple layers of conductive vias and conductive lines. The M1 metallization layer is typically the first major “wiring” layer that is formed on the product 10. Formation of the V0 and M1 conductive structures involves formation of a layer of insulating material 18 and an etch mask 19 comprised of first and second layers of material 20, 22. In one example, the layers of insulating material 14, 18 may be layers of so-called low-k (k value less than about 3.3) insulating material, the layer 16 may be a layer of silicon nitride, NBlok, etc., the layer 20 may be a TEOS-based layer of silicon dioxide, and the layer 22 may be a hard mask made of a metal, such as titanium nitride. The thickness of these various layers of material may vary depending upon the particular application.
FIG. 1A depicts the product 10 after several process operations have been performed. First, using known photolithography and etching techniques, a patterned photoresist mask (not shown) was formed above the product 10 and the mask layer 19 was patterned as depicted. Thereafter, the photoresist mask was removed and one or more etching processes were performed through the patterned mask layer 19 to form the depicted via openings 24 through the layers 18, 16 so as to expose the underlying conductive contact 12.
After the openings 24 are formed as depicted in FIG. 1A, the metal hard mask layer 22 is removed. FIG. 1B depicts the product 10 after another etching process, such as a wet etching process, was performed to remove the metal hard mask layer 22. Unfortunately, during this etching process, portions of the barrier layer 12A are also attacked and consumed, as reflected by the loss of the material of the barrier layer 12A within the enclosed dashed lines 23. In some cases, such as where the barrier layer 12A and the metal hard mask layer 22 are made of the same material, the problem may be more pronounced. Loss of barrier layer 12A materials can result in problems such as undesirable migration of materials from the bulk conductive material 12B into the insulating layer 14 and the creation of undesirable voids when subsequently formed conductive structures are formed above the damaged regions 23.
FIGS. 2A-2B depict another illustrative prior art method of forming conductive structures between metallization layers of an integrated circuit product using a damascene process. FIG. 2A depicts the integrated circuit product 10 wherein a M1 metallization layer 31 is formed in the layer of insulating material 14. In the depicted example, a metal line 30 is formed in the layer of insulating material 14. Typically, the metal line 30 is comprised of one or more barrier layers or liners 30A, e.g., tantalum/tantalum nitride, cobalt/tantalum nitride, ruthenium/tantalum nitride, and a bulk conductive material 30B, e.g., copper. In this example, a selectively deposited conductive cap layer 32, e.g., cobalt or manganese, is formed above the bulk conductive material 30B. As before, the etch stop layer 16 is formed above the layer of insulating material 14. Thus, another metallization layer 33, e.g., the M2 metallization layer, is formed above the M1 metallization layer 31. In the depicted example, formation of the metallization layer 33 involves the formation of a conductive via (V1) and an illustrative metal line of the M2 metallization layer. Formation of the V1 and M2 conductive structures involves formation of the above-described layer of insulating material 18 and etch mask 19 comprised of the first and second layers of material 20, 22.
FIG. 2A depicts the product 10 after several process operations have been performed. First, using known photolithography and etching techniques, a patterned photoresist mask (not shown) was formed above the product 10 and the mask layer 19 was patterned as depicted. Thereafter, the photoresist mask was removed and one or more etching processes were performed through the patterned mask layer 19 to form the depicted via openings 24 through the layers 18, 16 so as to expose the underlying metal line 30.
After the openings 24 are formed as depicted in FIG. 2A, the metal hard mask layer 22 is removed. FIG. 2B depicts the product 10 after another etching process, such as a wet etching process, was performed to remove the metal hard mask layer 22. Unfortunately, during this etching process, portions of the conductive cap layer 32 are also attacked and consumed, as reflected by the loss of the material of the conductive cap layer 32, as indicated by the arrow 34. Loss of material of the conductive cap layer 32 when subsequently formed conductive structures are formed above the damaged regions 34 can also be problematic, as noted above. Another problem is moisture can be absorbed by a ULK layer of insulating material 14 when it is exposed to a wet etch process. The moisture will increase the k value of the layer of insulating material 14 and can adversely impact TDDB.
The present disclosure is directed to various methods of forming conductive structures using a sacrificial material during the process of removing a metal hard mask layer used in forming such conductive structures that may solve or at least reduce some of the problems identified above.